FPGA-area Allocation for Partial Run-Time Reconfiguration

Although the new generations of FPGAs provide support for partial and dynamic configuration, the huge reconfiguration latency is still a major shortcoming of the current FCCMs . Software and hardware techniques (compiler optimizations, configuration prefetching) have been used in order to reduce the impact of the configuration overhead on the overall performance. Nevertheless, these techniques may not produce significant performance improvements when the hardware implementations of the operations executed on the FPGA are not properly placed on the target FPGA. For example, when three configurations should be placed on the target FPGA but only two of them can fit in the available FPGA area, then the placement of the third tasks will overlap at least with one other configuration. In such cases, a strategy is required to determine the optimal tasks placement on the target FPGA. In this paper, we propose two FPGA-area allocation algorithms for the tasks executed on the reconfigurable hardware. The goal is to minimize the FPGA-area which is reconfigured at runtime, taking into account the application runtime features. More specifically, we use the reconfiguration frequency for the target application to guide the allocation algorithms. Two scenarios are discussed: the first one corresponds to the case when all hardware operations must be placed/executed on the target FPGA while in the second scenario, a hardware operation can be switched to its pure software execution on the core processor in order to reduce the pressure/competition for the FPGA area. The FPGAarea allocation problem is formulated as a 0-1 integer linear programming (LP) problem and efficient LP solvers are used for finding the optimal solutions.